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Efficient synthetic traffic models for large, complex SoCs
2016
2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)
The interconnect or network on chip (NoC) is an increasingly important component in processors. As systems scale up in size and functionality, the ability to efficiently model larger and more complex NoCs becomes increasingly important to the design and evaluation of such systems. Recent work proposed the "SynFull" methodology that performs statistical analysis of a workload's NoC traffic to create compact traffic generators based on Markov models. While the models generate synthetic traffic,
doi:10.1109/hpca.2016.7446073
dblp:conf/hpca/YinKPJL16
fatcat:fd4fgvheendr7gegehz7ejn72m