Caching Techniques for Security Metadata in Integrity-Protected Fabric-Attached Memories

Mazen Alwadi, Amro Awad
2018 EAI Endorsed Transactions on Security and Safety  
The constant need for larger memories and the diversity of workloads have drove the system vendors away from the conventional processor-centric architecture into a memory-centric architecture. Memorycentric architecture, allows multiple computing nodes to connect to a huge shared memory pool and access it directly. To improve the performance, each node uses a small local memory to cache the data. These architectures introduce several problems when memory encryption and integrity verification
more » ... implemented. For instance, using a single integrity tree to protect both memories can introduce unnecessary overheads. Therefore, we propose Split-Tree, which implements a separate integrity tree for each memory. Later, we analyze the system performance, and the security metadata caches behavior when separate trees are used. We use the gathered insights to improve the security metadata caching for the separate trees and ultimately improve the system performance. command format and standards to be able to access the fabric-attached memory. While Gen-Z is perhaps the de facto standard for FAM architectures, many new protocols advocate for similar directions, e.g., Compute Express Lanes (CXL) [2] and Cache Coherent Interconnect for Accelerators (CCIX) [1]. Such protocols introduce a new architecture where processing elements can access the shared memory pools without going through home processor as in conventional system architectures such as NUMA systems. As FAM architectures are expected to have huge memory pools, using DRAM as the main memory can be problematic due to the expensive power required for the frequent refresh operations and cooling. Therefore, FAM architectures are expected to use emerging Non-Volatile-Memories (NVM) as the main memory [3] . Emerging NVMs are promising replacement for DRAM in future computing systems [17, 18, 20] . Such NVMs feature high-density, ultra-low idle power, performance comparable to DRAM and persistency. On the other hand, NVMs have a limited write endurance and power consuming writes. Moreover, NVMs ability to retain data during power loss facilitates data remanance attacks. Therefore, NVMs are typically
doi:10.4108/eai.13-7-2018.165516 fatcat:e2kgfdfd5bhsrelfxnuw4axmsm