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Power-Aware Scheduling for Parallel Security Processors with Analytical Models
[chapter]
2005
Lecture Notes in Computer Science
Techniques to reduce power dissipation for embedded systems have recently come into sharp focus in the technology development. Among these techniques, dynamic voltage scaling (DVS), power gating (PG), and multipledomain partitioning are regarded as effective schemes to reduce dynamic and static power. In this paper, we investigate the problem of power-aware scheduling tasks running on a scalable encryption processor, which is equipped with heterogenous distributed SOC designs and needs the
doi:10.1007/11532378_33
fatcat:ebjelxhhafaolk3f5arajucr4i