Fully parallel comparator for the moduli set {2n,2n-1,2n+1}

Shiva Taghipour Eivazi, Mehdi Hosseinzadeh, Omid Mirmotahari
2011 IEICE Electronics Express  
A novel circuit based on sign detection is introduced in this paper which uses the subtraction for comparing two numbers without carrying out a full comparison and conversion. Thus, the proposed schema decreases the delay significantly using only a little redundant hardware in contrast to previous works. Also the time complexity of the new design has the best results comparing to the previous work.
doi:10.1587/elex.8.897 fatcat:quiw47rldncgbilqw75n2blihy