SIGARCH Computer Architecture News
Detecting data races in parallel programs is important for both software development and production-run diagnosis. Recently, there have been several proposals for hardware-assisted data race detection. Such proposals typically modify the L1 cache and cache coherence protocol messages, and largely lose their capability when lines get displaced or invalidated from the cache. To avoid these shortcomings, this paper proposes a novel approach to hardwareassisted data race detection. The approach,
... n. The approach, called SigRace, relies on hardware address signatures. As a processor runs, the addresses of the data that it accesses are automatically encoded in signatures. At certain times, the signatures are automatically passed to a hardware module that intersects them with those of other processors. If the intersection is not null, a data race may have occurred. This paper presents the architecture of SigRace, an implementation, and its software interface. With SigRace, caches and coherence protocol messages are unmodied. Moreover, cache lines can be displaced and invalidated with no effect. Our experiments show that SigRace is signicantly more effective than a state-ofthe-art conventional hardware-assisted race detector. SigRace nds on average 29% more static races and 107% more dynamic races. Moreover, if we inject data races, SigRace nds 150% more static races than the conventional scheme.