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Embedding test patterns into Low-Power BIST sequences
2007
13th IEEE International On-Line Testing Symposium (IOLTS 2007)
Current trends in VLSI designs necessitate low power during both normal system operation and testing activity. Traditional Built-in Self Test (BIST) generators rise the power and energy consumption during testing, boosting the need to add low-power solutions to the arsenal of BIST pattern generators. In this work, the utilization of gray code generators is proposed as a low-power BIST solution; more precisely, we propose an algorithm to embed a test pattern into a sequence generated by a gray
doi:10.1109/iolts.2007.29
dblp:conf/iolts/Voyiatzis07
fatcat:fn4e5mlqg5hl7dl6kgxw3ooalu