Stretching the capacity of hardware transactional memory in IBM POWER architectures

Ricardo Filipe, Shady Issa, Paolo Romano, João Barreto
2019 Proceedings of the 24th Symposium on Principles and Practice of Parallel Programming - PPoPP '19  
The hardware transactional memory (HTM) implementations in commercially available processors are significantly hindered by their tight capacity constraints. In practice, this renders current HTMs unsuitable to many real-world workloads of in-memory databases. This paper proposes SI-HTM, which stretches the capacity bounds of the underlying HTM, thus opening HTM to a much broader class of applications. SI-HTM leverages the HTM implementation of the IBM POWER architecture with a software layer to
more » ... offer a single-version implementation of Snapshot Isolation. When compared to HTM- and software-based concurrency control alternatives, SI-HTM exhibits improved scalability, achieving speedups of up to 300% relatively to HTM on in-memory database benchmarks.
doi:10.1145/3293883.3295714 dblp:conf/ppopp/FilipeI0019 fatcat:k7rc6vxamfg37ffq7zennhfhxi