Analyzing hierarchical complex real-time systems

Yang Liu, Jun Sun, Jin Song Dong
2010 Proceedings of the eighteenth ACM SIGSOFT international symposium on Foundations of software engineering - FSE '10  
Specification and verification of real-time systems are important research topics which have practical implications. In this work, we present a self-contained toolkit to analyze real-time systems, which supports system modeling, animated simulation and automatic verification (based on advanced model checking techniques like dynamic zone abstraction). In this tool, we adopt an eventbased modeling language for describing real-time systems with hierarchical structure. Experiments show that our
more » ... has compatible performance with the state-of-the-art verifiers, and complement them with additional capabilities like LTL model checking, refinement checking. OVERVIEW AND SYSTEM DESIGN Ensuring the correctness of life-critical applications is crucial and challenging. This is especially true when the correctness of such systems depends on quantitative timing. The state-of-the-art approach for specifying real-time systems is based on the notation Timed Automata (TA) [1]. TA often have a flat structure, e.g. a network of TA with no hierarchy, which makes the efficient model checking feasible. Nonetheless, designing and verifying compositional real-time systems is becoming an increasingly difficult task. High-level requirements for real-time systems are often stated in terms of deadline, time out, and timed interrupt. Unlike statecharts with clocks or timed process algebras, TA lack these compositional patterns. As a result, users often need to manually cast those terms into a set of clock variables with carefully calculated clock constraints. The process is tedious and error-prone. To solve this problem, we proposed an alternative approach [6] for modeling and verifying hierarchical real-time systems. Based on process algebra, our modeling language introduces a rich set of concurrent operators and compositional timed behavioral patterns like deadline, within, timed interrupt, etc. Instead of explicitly manipulating clock variables (as in TA), the timed patterns are designed to build on implicit clocks. Further, we augment a system model with mutable variables and data structures (e.g., arrays, *
doi:10.1145/1882291.1882350 dblp:conf/sigsoft/LiuSD10 fatcat:7bt5ap6f2fdilet7knsrhnvm7m