Formal verification using parametric representations of Boolean constraints

Mark D. Aagaard, Robert B. Jones, Carl-Johan H. Serger
1999 Proceedings of the 36th ACM/IEEE conference on Design automation conference - DAC '99  
We describe the use of parametric representations of Boolean predicates to encode data-space constraints and significantly extend the capacity of formal verification. The constraints are used to decompose verifications by sets of case splits and to restrict verifications by validity conditions. Our technique is applicable to any symbolic simulator. We illustrate our technique on state-of-the-art Intel (R) designs, without removing latches or modifying the circuits in any way. _ ___________________________
doi:10.1145/309847.309968 dblp:conf/dac/AagaardJS99 fatcat:szvd5ykjgzd3nn4gp4xejvhlbu