A comprehensive SoC design methodology for nanometer design challenges

R.R. Kumar, R. Bedi, R. Rajagopal, N. Guruprasad, K. Subbarangaiah, T. Abbasi, D.V.R. Murthy, P.K. Prasad, D.R. Gude
2006 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06)  
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex design challenges in silicon which were not seen in higher geometries. The most commonly talked about factor is the dominance of interconnects over cell delays for long nets. Also leakage power at sub-nanometer levels is becoming a major component of the total chip power. Cross-coupling capacitance is starting to
more » ... e and signal integrity methodologies and sign-off have become mandatory part of all sub-nanometer flows. Methodologies which can address capacity issues have also become mandatory with average design sizes crossing 10M gates for sub-nanometer processes. Traditional bottom-up based approaches alone will not suffice to handle this kind of capacity. Finally another prime factor is related to manufacturability and dealing with process variations to ensure maximum yield. In fact optimization for yield is something which is beginning to be considered from the synthesis phase.
doi:10.1109/vlsid.2006.7 dblp:conf/vlsid/KumarBRGSAMPG06 fatcat:gg3e3zqiojcnlect4hswlyntsy