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SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex design challenges in silicon which were not seen in higher geometries. The most commonly talked about factor is the dominance of interconnects over cell delays for long nets. Also leakage power at sub-nanometer levels is becoming a major component of the total chip power. Cross-coupling capacitance is starting todoi:10.1109/vlsid.2006.7 dblp:conf/vlsid/KumarBRGSAMPG06 fatcat:gg3e3zqiojcnlect4hswlyntsy