Thesis Overview: AES development in FPGA

M Liberatori
2006 unpublished
The importance of cryptography applied to security in electronic data transactions has acquired an essential relevance during the last years. Each day millions of users generate and interchange large volumes of information in various fields, such as financial and legal files, medical reports, bank services via Internet, telephone conversations, and e-commerce transactions. These and other examples of applications deserve a special treatment from the security point of view, not only in the
more » ... ort of such information but also in its storage. In this sense, cryptography techniques. use is especially applicable. Many have been the proposals made to establish implementation standards applicable to the two large branches of cryptography: symmetric key and public key. During many years, one of them-Data Encryption Standard (DES). mastered the area of symmetric-key cryptography. Technological advances, as regards data processing speed, placed DES in a vulnerable position due to the size of its key. This triggered its replacement as standard. The National Institute of Standards and Technology (NIST) created a new standard known as Advanced Encryption Standard (AES), with the objective of developing the Federal Information Processing Standard (FIPS) which specifies an encryption algorithm capable of protecting sensitive information to be used by the government of the United States. In October 2000, the NIST selected Rijndael as the algorithm proposed for the AES. The algorithm has a round shape made up by three uniform and non-reversible transformations which assures broadcast over the total set of fixed rounds and optimal non-linearity properties. This thesis presents an 8-bit FPGA implementation of the 128-bit block and 128 bit-key AES cipher. The aim of this thesis is focused on Rijndael.s encryption phase, particularly its development in VHDL hardware description language and its synthesis for the implementation over FPGA, minimizing the necessary hardware resources. Since the objectives of minimizing the area to be used and maximizing the processing speed are opposed, it is necessary to select a suitable architecture for the aim pursued.