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BIST Based Interconnect Fault Location for FPGAs
[chapter]
2004
Lecture Notes in Computer Science
This paper presents a novel approach to interconnect fault location for FPGAs during power-on sequence. The method is based on a concept known as fault grading which utilizes defect knowledge during manufacturing test to classify faulty devices into different defect groups. A Built-In Self-Test (BIST) method that can efficiently identify the exact location of the interconnect fault is introduced. This procedure forms the first step of a new interconnect defect tolerant scheme that offers the
doi:10.1007/978-3-540-30117-2_34
fatcat:eysjqfqnkrcqplgbt73jn3osdy