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Multiprocessing (MP) design verification has been one of the bottlenecks for high performance microprocessor design projects. The problem is getting worse as the design complexity increases and more cache structures are integrated into one single chip. The challenges that MP verification faces today include: huge chip/system simulation model sizes, long simulation cycles, relative inefficiency of the simulation tools compared to uniprocessor, and so on. To solve these challenging problems, wedoi:10.1145/337292.337755 dblp:conf/dac/YenY00 fatcat:oshzysltpnfflpzkatdu6h6qvm