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SSTL IO Standard Based Low Power Arithmetic Design Using Calana Kalanabhyam on FPGA
2016
International Journal of Control and Automation
Vedic mathematics consists of 16 formulas. Calanakalanabhyam is a Sanskrit word meaning "Sequential motion". Using this Vedic technique, we will find the roots of the equation in few seconds. We have tried to make an energy efficient Calanakalanabhyam Vedic formula based root finder with 4 inputs and 2 outputs. We have taken different SSTL Input/Output Standards and have done Study of Power by varying frequencies. SSTL Input/Output Standards used in this paper are SSTL15, SSTL18_II, SSTL135,
doi:10.14257/ijca.2016.9.4.27
fatcat:7juxbnmjdzc2fckicv3jjcjytu