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Leveraging on-chip DRAM stacking in an embedded 3D multi-core DSP system
2011
2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS)
Embedded multi-core systems are gaining popularity for many embedded applications. Compared to the multicore design for general purpose high performance computing, the memory design for an embedded multi-core processor should be customized and adapt to embedded application's characteristics, because it usually has significant impact on the system performance. In this paper, we study a 3D embedded multi-core DSP processor called 3D-iSPA, which is targeted for multimedia applications with two
doi:10.1109/mwscas.2011.6026431
fatcat:3elt2y6gx5cu5absi6uhvjezt4