A PTL Based Full Adder Design using Cadence

Priyadarshini N J
2020 International Journal for Research in Applied Science and Engineering Technology  
In recent days, demand for VLSI or ULSI has been improved drastically due to its robustness and efficiency. Due to peoples' demand of having miniature device with more battery life the VLSI Engineers are trying to innovate the existing designs by slightly modifying the pre-existing one. One of such examples is to use pass transistor logic, which has tremendous advantage over all other logics. Thus by exploiting the architecture of such logics may give rise to a device which satisfies all the
more » ... atisfies all the demands of the market. In this work, the design of a low power and area efficient hybrid full adder is proposed which uses the pass transistor logic. The circuit has been designed and tested using minimum number of CMOS elements. The implementation of the design has been made in 180nm technology in CADENCE tool and it is simulated various times for numerous test cases. Also the design has been compared with the previously existing works. Thus the simulated results show the effectiveness in terms of area, speed and power dissipation.
doi:10.22214/ijraset.2020.30853 fatcat:sedytspjpzbq5m225ezgysys7m