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Hf-based charge-trapping (CT) layers, including HfO 2 and HfAlO, were employed in the fabrication of a CT-type memory with gate-all-around (GAA) poly-Si nanowire channels. It is shown that the GAA configuration can greatly enhance the programming/erasing efficiency as compared with the conventional planar scheme. It is also shown that the incorporation of Al into the dielectric can further improve the retention and endurance characteristics over the counterparts with a HfO 2 trapping layer.doi:10.1109/led.2013.2237748 fatcat:bcc6mlb4nnhllkkkuy5aph4wqu