In this paper, a new normalization design method for floating-point unit is presented. Shift amount information for normalization is devised to generate leading one position value (LOPV). LOPV is the number with all bits zero except the leading one position. LOPV can be easily generated by two NOR planes, which implies it can be implemented by bitparallel operations. Therefore, LOPV can be acquired within about a half delay time of conventional leading zero counters (LZC). An additional NOR

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... e is required to decode the LOPV to shifter control signals. Total three NOR planes and actual shifter operation can implement the floating-point normalization. The chip has been fabricated by using a commercial TSMC 0.18µm 5-metal CMOS technology with 1.8V supply voltage. The core area is 550µm x 200µm and normalization delay has been measured as 1.4ns.