Geometric Tiling for Reducing Power Consumption in Structured Matrix Operations

G. Chen, L. Xue, J. Kim, K. Sobti, L. Deng, X. Sun, N. Pitsianis, C. Chakrabarti, M. Kandemir, N. Vijaykrishnan
2006 2006 IEEE International SOC Conference  
This work focuses on reducing power consumption while maintaining the efficiency and accuracy of matrix computations using both algorithmic and architectural means. We transform the algorithms, in adaptation to application specifics, to translate the matrix structures into power saving potential via geometric tiling. Instead of using blind tiling, we index and partition matrix elements according to the underlying geometry to claim a better estimate and control of numerical range within and
more » ... s geometric tiles, which can then be exploited for power saving.
doi:10.1109/socc.2006.283861 dblp:conf/socc/ChenXKSDSPCKV06 fatcat:bhxvspngnfb5lockmhcdqtyqtm