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This work focuses on reducing power consumption while maintaining the efficiency and accuracy of matrix computations using both algorithmic and architectural means. We transform the algorithms, in adaptation to application specifics, to translate the matrix structures into power saving potential via geometric tiling. Instead of using blind tiling, we index and partition matrix elements according to the underlying geometry to claim a better estimate and control of numerical range within anddoi:10.1109/socc.2006.283861 dblp:conf/socc/ChenXKSDSPCKV06 fatcat:bhxvspngnfb5lockmhcdqtyqtm