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A generic architecture for on-chip packet-switched interconnections
2000
Proceedings of the conference on Design, automation and test in Europe - DATE '00
This paper presents an architectural study of a scalable system-level interconnection template. We explain why the shared bus, which is today's dominant template, will not meet the performance requirements of tomorrow's systems. We present an alternative interconnection in the form of switching networks. This technology originates in parallel computing, but is also well suited for heterogeneous communication between embedded processors and addresses many of the deep submicron integration
doi:10.1145/343647.343776
fatcat:7wk4mgcy5rcwpox6ajnqi4rykm