Design and Testing of 16 bit Carry Save Adder using Reconfigurable LFSR

2020 International Journal of Advanced Trends in Computer Science and Engineering  
In this paper, the design and testing of Carry Save Adder (CSA) using Reconfigurable LFSR is implemented. The ever increasing applications of integrated circuits in the day-to-day useful electronic gadgets are the driving force for the development of low power designs of configurable hardware designs. High speed and low power are the main parameters that are targeted by modern circuit designers. Among the fastest increasing applications, the audio and video signal processing applications are
more » ... wing at a very high rate. Mobile applications have increased the technological improvements for digital signal processing applications. Arithmetic functions are the very important logical operational unit of any processing unit in digital signal processing applications. The speed of arithmetical computations and performance is among the parameters of any digital hardware design for efficiency improvement. Self-testing ability is another essential aspect of hardware design. This feature offers hardware durability primarily for hardware applications that can be configured. The builtin-self test (BIST) feature helps in the quick diagnosis of the hardware functional authenticity. This paper introduces a carrying save adder with BIST included in it. The work is developed using the Verilog HDL language and implemented in Xilinx Vivado. The concept of self-test design requires a low power test pattern generator (TPG).
doi:10.30534/ijatcse/2020/156952020 fatcat:fg4znbugd5gbpb2izyvea2ejta