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<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/k4pq3zhykrd3hdhey2qhybwinu" style="color: black;">2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)</a>
True random number generator (TRNG), plays an important role in information security systems. Conventional TRNGs use natural physical stochastic processes including thermal noise, chaos-based circuit and so on to generate the random numbers. These analog circuit based TRNG structures often consume lots of hardware resources, and are not easy to be integrated in digital systems. In this paper, a low-cost and high-speed TRNG has been proposed by using mixed oscillation generated from XOR gates<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/isvlsi.2018.00079">doi:10.1109/isvlsi.2018.00079</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/isvlsi/MeiZGCWL18.html">dblp:conf/isvlsi/MeiZGCWL18</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/57ikl4wbsjbybdupffcgq62qgi">fatcat:57ikl4wbsjbybdupffcgq62qgi</a> </span>
more »... ted multiple ring oscillators (ROs). Multi-group mixed oscillation XOR operation is applied to obtain high-speed output. The proposed TRNG design is implemented on Xilinx Artix-7 XC7A35T-1FTG256C FPGA. It achieves a high performance with throughput up to 160 Mbps and with a usage of 37 FFs and 25 look up tables (LUTs) in the FPGA. The results show that the proposed TRNG design has successfully passed the testing standards of NIST SP800-22 and AIS31. Compared with previous designs, the proposed TRNG design achieves lower hardware resource consumption and higher speed.
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