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RISC-V Based Safety System-on-Chip with Hardware Comparator
[chapter]
2021
Frontiers in Artificial Intelligence and Applications
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In this paper, a Safety System-on-Chip based on the open-source RISC-V processor SweRV EH1 from Western Digital is presented. A hardware comparator concept is followed. The SSoC is implemented on a Xilinx FPGA system and extended with standard peripherals from the Xilinx IP library and from Cobham Gaisler, so that the overall system has an Ethernet interface in addition to GPIO and UART. The goal is to create a complete redundancy approach with a hardware fault tolerance of nearly 1 from input
doi:10.3233/faia210423
fatcat:prdd6twjzna4nh5u3d6zjml7xq