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At speed delay testing is important for embedded systems. Attempts to solve the problems of delay testing only with non-scan or scan-based tests are unsuccessful. There is no need to oppose these tests, but it is necessary to use both taking full advantage of their opportunities. Design flow and the ability to use non-scan and scan-based ATPG, functional test and fault simulation is presented. The goal is to detect as many faults with non-scan at-speed test. The remaining faults are detecteddoi:10.11648/j.cssp.20160502.11 fatcat:h4zvupuvxbfdtj6xmlyqud5qb4