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Although directory-based write-invalidate cache coherence protocols have a potential to improve the performance of large-scale multiprocessors, coherence misses limit the processor utilization. Therefore, so called competitive-update protocols -hybrid protocols that on a per block basis dynamically switch between write-invalidate and write-update -have been considered as a means to reduce the coherence miss rate and have been shown to be a better coherence policy for a wide range ofdoi:10.1006/jpdc.1996.0164 fatcat:a6a6nrmkrfcmbjvyz7jwxgjniq