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Variational capacitance extraction of on-chip interconnects based on continuous surface model
2009
Proceedings of the 46th Annual Design Automation Conference on ZZZ - DAC '09
In this paper we present a continuous surface model to describe the interconnect geometric variation, which improves the currently used model for better accuracy while not increasing the number of variables. Based on it, efficient techniques are presented for chip-level capacitance extraction considering the window technique. The sparse-grid-based Hermite polynomial chaos combined with a novel weighted principle factor analysis is employed for intra-window extraction. Then, the inter-window
doi:10.1145/1629911.1630108
dblp:conf/dac/YuHZ09
fatcat:oojw56r7tngbvkvfx2q72x25nq