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A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation
2007
2007 Asia and South Pacific Design Automation Conference
Exceptionally leaky transistors are increasingly more frequent in nano-scale technologies due to lower threshold voltage and its increased variation. Such leaky transistors may even change position with changes in the operating voltage and temperature, and hence, redundancy at circuit-level is not sufficient to tolerate such threats to yield. We show that in SRAM cells this leakage depends on the cell value and propose a first software-based runtime technique that suppresses such abnormal
doi:10.1109/aspdac.2007.358100
dblp:conf/aspdac/GoudarziIY07
fatcat:giexcx6iijd4hchr7vm37uecjq