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Hardware implementation issues of turbo decoders
2012
Bangladesh Journal of Scientific and Industrial Research
This paper gives a general overview of the implementation aspects of turbo decoders. Although the parallel architecture of the turbo code is emphasized, the serial concatenated convolutional codes for the turbo decoder are discussed too. Considering the general structure of iterative decoders, the main features of the soft input and soft output algorithm, which are the heart of a turbo decoder, are observed. The efficient parallel architectures of turbo decoders are shown which allow high speed
doi:10.3329/bjsir.v47i3.13068
fatcat:h7setklwtrhndbcocwdss4v7yy