Nowadays, there are growing trends of advances in wireless devices and becoming common in every household and workplace. The increasing desire for these devices is to create smaller, fast, and low power applications. The growing need in today's wireless applications is increasing requirements for identification of a high-speed low noise, low power novel Phase-locked loop (PLL) design. The PLL feedback loop can be found in nearly all aspects of wireless communication, these include radio, TV,

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... l phones, PDAs, pagers, wireless transmitters and receivers, etc. Phase-locked loop (PLL) is a feedback control system that generates an output signal whose frequency and phase depends on the phase of the input signal, the main PLL building blocks are; Phase Frequency Detector (PFD), Charge Pump (CP), Loop Filter (LF), Voltage Controlled Oscillator (VCO), and Frequency Divider (FD). This paper addresses a wide tuning range "2.4-5.0 GHz", novel high-frequency PLL design for wireless applications. The theoretical model and PLL analysis are principally described in the theoretical part. While, in the practical part, the design choices of various blocks, design calculation and simulation for final solutions are presented. The novel designed solution is simulated using 22nm CMOS technology, SPICE simulation software is used to evaluate the theoretical basics and fundamentals, and the final result are commented.