A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2018; you can also visit the original URL.
The file type is application/pdf
.
An improved low power Viterbi decoder in System-on-Chips
2017
Proceedings of the 2nd Annual International Conference on Electronics, Electrical Engineering and Information Science (EEEIS 2016)
unpublished
The (2,1,7) convolutional codes have become the standard encoding method of satellite communication system. Based on an optimized structure, a low power (2,1,7) Viterbi decoder with trace-back length of 32 is presented in this paper. New structure of addcompare-select(ACS) unit is exploited to reduce power consumption. Instead of using register-exchange(RE) and register banks, trace-back that consumes less power and the power-saving RAM are used. Our proposed Viterbi decoder consumes about
doi:10.2991/eeeis-16.2017.39
fatcat:mfgoo5dyf5e2vff6fwhzuxwgfu