A Hardware-Efficient Pattern Matching Architecture Using Process Element Tree for Deep Packet Inspection

Seongyong AHN, Hyejeong HONG, HyunJin KIM, Jin-Ho AHN, Dongmyong BAEK, Sungho KANG
<span title="">2010</span> <i title="Institute of Electronics, Information and Communications Engineers (IEICE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/4dhg4rk2rzdyfllkpx64b2rq6a" style="color: black;">IEICE transactions on communications</a> </i> &nbsp;
This paper proposes a new pattern matching architecture with multi-character processing for deep packet inspection. The proposed pattern matching architecture detects the start point of pattern matching from multi-character input using input text alignment. By eliminating duplicate hardware components using process element tree, hardware cost is greatly reduced in the proposed pattern matching architecture. key words: network intrusion detection system, deep packet inspection, pattern matching, brute-force algorithm
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1587/transcom.e93.b.2440">doi:10.1587/transcom.e93.b.2440</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/unoo26b6qnakrm6p65cjhsy2ge">fatcat:unoo26b6qnakrm6p65cjhsy2ge</a> </span>
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