A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf
.
A 10-Bit 300-MS/s Pipelined ADC With Digital Calibration and Digital Bias Generation
2013
IEEE Journal of Solid-State Circuits
A 10-bit pipelined ADC was fabricated using a 65 nm CMOS technology. To reduce power consumption, switching opamps are used. These switching opamps are designed to have a short turn-on time. Digital background calibration is employed to correct the A/D conversion error caused by the low dc gain of the opamps. The biasing voltages in each opamp are automatically generated using digital circuits. This bias scheme can maintain the settling behavior of the opamp against process-voltage-temperature
doi:10.1109/jssc.2012.2233332
fatcat:meu5nxms2vgqhajy7uesg256m4