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Energy efficient semiconductor chips are in high demand to cater the needs of today's smart products. Advanced technology nodes insert high design margins to deal with rising variations at the cost of power, area and performance. Existing run time resilience techniques are not cost effective due to the additional circuits involved. In this paper, we propose a design time resilience technique using a clock stretched flip-flop to redistribute the available slack in the processor pipeline to thedoi:10.1109/vlsi-soc.2016.7753570 dblp:conf/vlsi/JayakrishnanCK16 fatcat:zsq26ctmwjeetalfsdjjf2iuhm