The Promise of High-Performance Reconfigurable Computing
High-performance Reconfigurable Computers (HPRCs) integrate nodes of either microprocessors and/or field programmable gate arrays (FPGAs) through an interconnection network and system software into a parallel architecture. For domain scientists who lack the hardware design experience, programming these machines is near impossible. Existing high-level programming tools such as C-tohardware tools only address designs on one chip. Other tools require the programmer to create separate hardware and
... oftware program modules. An application programmer needs to explicitly develop the hardware side and the software side of his/her application separately and figure out how to integrate the two in order to achieve intra-node parallelism. Furthermore, the programmer will have to follow that with an effort to exploit the extra-node parallelism. In this work, we propose unified parallel programming models for HPRCs based on the Unified Parallel C programming language (UPC). Through extensions to UPC, the programmer is presented with a programming model that abstracts hardware microprocessors and accelerators through a two level hierarchy of parallelism. The implementation is quite modular and capitalizes on the use of source-tosource UPC compilers. Based on the parallel characteristics exhibited at the UPC program, code sections that are amenable to hardware implementation are extracted and diverted to a C-tohardware compiler. In addition to extending the UPC specifications to allow hierarchical parallelism and hardware-software co-processing, a framework is proposed for calling and using an optimized library of cores as an alternative programming model for additional enhancement. Our experimental results will show that the proposed techniques are promising and can help non-hardware specialists to program HPRCs with substantial ease while achieving improved performance in many cases.