Instruction scheduling for power reduction in processor-based system design

H. Tomiyama, T. Ishihara, A. Inoue, H. Yasuura
Proceedings Design, Automation and Test in Europe  
Abstract| This paper propose an instruction scheduling technique to reduce power consumed for o-chip driving. The technique minimizes the switching activity of a data bus between an on-chip cache and a main memory when instruction cache misses occur. The scheduling problem is formulated and a scheduling algorithm is also presented. Experimental results demonstrate the eectiveness and the eciency of the proposed algorithm. Main memory (DRAM) Processor CPU core Cache Address bus Data bus Off-chip
more » ... s Data bus Off-chip drivers
doi:10.1109/date.1998.655958 dblp:conf/date/TomiyamaIIY98 fatcat:hbsw5z3k2jba3orbmjkwlndy5y