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31st Annual Conference of IEEE Industrial Electronics Society, 2005. IECON 2005.
This paper analyzes the performance and timing overhead trade-off for a recently proposed data bus encoding scheme for low-power based on data lines reordering. The Bus Switch (BS) mechanism introduces greater activity savings than previous approaches; the hardware complexity of the encoder suggests to apply BS in off-chip buses, where the parasitic capacitance makes dynamic power dissipation in the bus lines the dominant contribution to power consumption. In the basic BS implementation, thedoi:10.1109/iecon.2005.1569251 fatcat:ayxg4ozh7jhcpj23uazjygz7ja