Instruction Trace Compression for Rapid Instruction Cache Simulation

Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran, Joerg Henkel
2007 2007 Design, Automation & Test in Europe Conference & Exhibition  
proposed in the past to reduce the size of these program trace files. Modern Application Specific Instruction Set Processors (ASIPs) have Although compression allows the reduction of the program trace file customizable caches, where the size, associativity and line size can size, the required intermediate memory during decompression and all be customized to suit a particular application. To find the best program trace analysis is still large, requiring enormous number of cache size suited for a
more » ... particular embedded system, the applica-reads and writes to disks. tion(s) is/are executed, traces obtained, and caches simulated. Typi-In this paper, we present a novel method to allow cache simulacally, program trace files can range from a few megabytes to several tion to be performed from a compressed program trace file such that gigabytes. Simulation of cache performance using large program only 'partial decompression' is necessary. Our experimental results trace files is a time consuming process. In this paper, a novel in-showed that our cache simulation methodology is on average 9.67 struction cache simulation methodology that can operate directly on times faster compared to the existing state-of-the-art cache simua compressed program trace file without the need for decompres-lation tool. To compress the program trace file, we developed a sion is presented. This feature allowed our simulation methodology compression methodology that allows for random access decompresto have an average speed up of 9.67 times compared to the exist-sion [3]. Random access decompression is a term used to describe a ing state of the art tool (Dinero IV cache simulator), for a range of compression methodology that allows the decompression to start at applications from the Mediabench suite. any point in the compressed file. The random access decompression feature allows our cache simulation methodology to operate on the
doi:10.1109/date.2007.364389 dblp:conf/date/JanapsatyaIPH07 fatcat:ilg7vb2tgzfxhil6tj7fawi4jm