A multiplier is one of the chief hardware blocks in most digital and high concert systems such as microprocessors, digital signal processors, etc. In this paper 4×4 as well as 8×8 Array, Wallace and Vedic multipliers structural design is being designed. Among these three types of multipliers Vedic multiplier base on Vedic arithmetic using Urdhva-Tiryabhyam sutra are proved to be the most efficient in terms of lower power consumption. In MOSFET by applying a shrinking technology below 100nm

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... es a key challenge for power chip management so to overcome these limitations the CNTFET are introduced, and due to this comparison of multipliers are made between MOSFET 32nm and CNTFET 32nm technology. The CNFET-based multipliers have higher speed, and low power dissipation and it nearly reduces 99% PDP (power-delay product) as compared to the MOSFET. And still to reduce the power consumption the low power technique such as MTCMOS is used and all the three different designs of 4×4 as well as 8x8 multipliers are designed using the Multi-Threshold Voltage CMOS (MTCMOS) it proved to be best among all the implementations. And it nearly reduces 50% of power compare to normal multipliers (i.e. without applying technique). The functionality of all the three designs is based on 32nm Berkeley Predictive Technology Model (BPTM) are calculated at 1v supply voltage and simulating them with hi-spice software.