Timing analysis of erroneous systems

Omid Assare, Rajesh Gupta
2014 Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis - CODES '14  
Erroneous systems allow timing errors to occur during execution, but use measures to ensure continued operation through changes in operating parameters (voltage and frequency), error correction at various levels of the system, or ensuring controlled occurrence of errors to perform approximate computing. In this paper, we are interested in characterization of error behavior at the level of instructions and programs. We propose Inter-and Intra-Program Variation as measures of error rate
more » ... y in different programs and among instructions of a program, respectively. We also characterize the error rate variation caused by the program input data and show that it is comparable to other sources of variability such as process variation. Finally, we present an analysis of the physical location of errors in hardware, identify regions in which most of the errors occur, and how different programs change the distribution of errors among these regions. In order to enable reliable timing analysis of large programs, we propose Clustered Timing Model (CTM), a high level timing model based on clustering functionally similar timing paths of the processor, and develop a CTM for LEON3, a representative in-order RISC processor. The accuracy of the model is verified using our variation-aware timing analysis framework with an average error of 3.9% (max. 6.7%) across a wide range of voltage-temperature corners.
doi:10.1145/2656075.2656101 dblp:conf/codes/AssareG14 fatcat:bskxaf6j5nfnbkj3ca537q6k6a