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A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion
2009
Proceedings of the 46th Annual Design Automation Conference on ZZZ - DAC '09
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimization, buffer insertion is indispensable in the physical synthesis flow. Buffering is known to be NP-complete and existing works either explore dynamic programming to compute optimal solution in the worst-case exponential time or design efficient heuristics without performance guarantee. Even if buffer insertion is one
doi:10.1145/1629911.1630026
dblp:conf/dac/HuLA09
fatcat:kls4bfjl2jgyvhnbtdqmvsge3e