A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf
.
A machine independent WCET predictor for microcontrollers and DSPs [worst case execution time]
ISIE 2001. 2001 IEEE International Symposium on Industrial Electronics Proceedings (Cat. No.01TH8570)
This paper describes a method for analyzing and predicting the timing properties of a program fragment. The paper first presents a little language implemented to describe a processor's architecture and a static WCET estimation method is then presented. The timing analysis starts by compiling a processor's architecture program followed by the disassembling of the program fragment. The assembler program is then decomposed into basic blocks and a call graph is generated. These data are later used
doi:10.1109/isie.2001.931609
fatcat:4p65qcyfircuzjaoudf4iz6nuq