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ISIE 2001. 2001 IEEE International Symposium on Industrial Electronics Proceedings (Cat. No.01TH8570)
This paper describes a method for analyzing and predicting the timing properties of a program fragment. The paper first presents a little language implemented to describe a processor's architecture and a static WCET estimation method is then presented. The timing analysis starts by compiling a processor's architecture program followed by the disassembling of the program fragment. The assembler program is then decomposed into basic blocks and a call graph is generated. These data are later useddoi:10.1109/isie.2001.931609 fatcat:4p65qcyfircuzjaoudf4iz6nuq