Multilevel symmetry-constraint generation for retargeting large analog layouts

S. Bhattacharya, N. Jangkrajarng, C.-J.R. Shi
2006 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
The strong impact of layout intricacies on analogcircuit performance poses great challenges to analog layout automation. Recently, template-based methods have been shown to be effective in reuse-centric layout automation for CMOS analog blocks such as operational amplifiers. The layout-retargeting method first creates a template by extracting a set of constraints from an existing layout representation. From this template, new layouts are then generated corresponding to new technology processes
more » ... nd new device specifications. For large analog layouts, however, this method results in an unmanageable template due to a tremendous increase in the number of constraints, especially those emerging from layout symmetries. In this paper, we present a new method of multilevel symmetry-constraint generation by utilizing the inherent circuit structure and hierarchy information from the extracted netlist. The method has been implemented in a layoutretargeting system called Intellectual Property Reuse-based Analog IC Layout (IPRAIL) and demonstrated 18 times reduction in the number of symmetry constraints required for retargeting an analog-to-digital converter layout. This enables our retargeting engine to successfully handle the complexities associated with large analog layouts. While manual relayout is known to take weeks, our layout-retargeting tool generates the target layout in hours and achieves comparable electrical performance. Index Terms-Analog integrated circuit (IC), device matching, IC layout, layout automation.
doi:10.1109/tcad.2005.855982 fatcat:tctvgcplzzej3n4x7ocgobuwdq