Paper Overview • Significance: current CMOS-based cache memories, SRAM and eDRAM, face the challenges of power consumption and scalability limit. Domain Wall Memory(DWM) has the benefit of high density, low power, and high access speed. • Challenges: The structure of DWM logically resembles a bit-serial tape. Thus, the data in DWM has to be sequentially accessed by performing "shift" operations, resulting in high access latencies. • Target: design a DWM-based cache hierarchies with optimized

more »

... ency and density. • Methods: L1 cache-> single-bit DWM, L2 cache's tag array-> single-bit DWM, L2 cache's data array->multiple-bits DWM. Multiple-bits DWM-> clustered bit-interleaved organization, tape-head management policy, shift aware promotion buffer. • Results: 12.1% and 5.8% performance benefit over SRAM and STT-MRAM; 3.3X and 2.6X energy saving over SRAM and STT-MRAM. Domain Wall Memory is a spin-based memory technology, which represents information using the spin orientation of the magnetic domains in a ferromagnetic wire. Read Operation: Like what STT-RAM does, the magnetic orientation of fixed layer and free layer determines the MTJ resistance. We can use the different resistance value as "1" and "0". The latency is very similar to SRAM, and the current is also much smaller compared to SRAM. BL RWL Background-Domain Wall Memory • Shift Operation: When a current pulse is applied through the ferromagnetic wire, the magnetic orientation of each domain is shifted in a direction opposite to the current. It is called as "domain wall motion". • Write Operation: STTRAM uses a large spin-torqued current to change the state of MTJ. But in domain wall memory, write operation based on shift costs less power and also even much faster. Two fixed domain with up-spin and downspin are attached to both sides of free domain. A shift operation with Iwrite0 and Iwrite1 decides the new status of free domain.