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Architectural decisions for DSP modules are often analyzed using high level C models. Such high-level explorations allow early examination of the algorithms and the architectural trade-offs that must be made for a practical implementation. The same models can be reused during the verification of the RTL subsequently developed, provided that various "hooks" which are desirable during the verification process are considered while creating these high level models. In addition, consideration mustdoi:10.1145/1146909.1146935 dblp:conf/dac/BrierM06 fatcat:g2fqqrxklnderlxjucbkusyfn4