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Architecture and Synthesis for On-Chip Multicycle Communication
2004
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
For multigigahertz designs in nanometer technologies, data transfers on global interconnects take multiple clock cycles. In this paper, we propose a regular distributed register (RDR) microarchitecture, which offers high regularity and direct support of multicycle on-chip communication. The RDR microarchitecture divides the entire chip into an array of islands so that all local computation and communication within an island can be performed in a single clock cycle. Each island contains a
doi:10.1109/tcad.2004.825872
fatcat:q3jbmcmtz5g2lccyfz2lirpzqa