Architecture and Synthesis for On-Chip Multicycle Communication

J. Cong, Y. Fan, G. Han, X. Yang, Z. Zhang
2004 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
For multigigahertz designs in nanometer technologies, data transfers on global interconnects take multiple clock cycles. In this paper, we propose a regular distributed register (RDR) microarchitecture, which offers high regularity and direct support of multicycle on-chip communication. The RDR microarchitecture divides the entire chip into an array of islands so that all local computation and communication within an island can be performed in a single clock cycle. Each island contains a
more » ... of computational elements, local registers, and a local controller. On top of the RDR microarchitecture, novel layout-driven architectural synthesis algorithms have been developed for multicycle communication, including scheduling-driven placement, placement-driven simultaneous scheduling with rebinding, and distributed control generation, etc. The experimentation on a number of real-life examples demonstrates promising results. For data flow intensive examples, we obtain a 44% improvement on average in terms of the clock period and a 37% improvement on average in terms of the final latency, over the traditional flow. For designs with control flow, our approach achieves a 28% clock-period reduction and a 23% latency reduction on average. 1 This is an update of the similar figure shown in [8] , which is based on NTRS'97 [32] . Optimal buffer insertion and wire sizing are performed using the IPEM [7] package with the driver, buffer, and receiver sizes being 100 2 the minimum size inverter.
doi:10.1109/tcad.2004.825872 fatcat:q3jbmcmtz5g2lccyfz2lirpzqa