Optimization of Control Block of 3-bit PWM using Adiabatic Dynamic CMOS Logic for OLED Illumination System Based on Internet of Things Service

Seung-Il Cho, Sung-Dae Yeo, Seong-Kweon Kim, Michio Yokoyama
2016 International Journal of Smart Home  
The environment development for deep sleep has been studied using analysis results of the big data about vital signs and parameters in the bedroom. The organic light emitting diode (OLED) illuminations of the bedroom are dimming using analysis results of the big data. Therefore, a low-power and compact design of dimming part is required for OLED illumination system. In this paper, the optimized control block of the clock cut-off circuit was designed using De Morgan's laws with adiabatic dynamic
more » ... h adiabatic dynamic CMOS logic (ADCL) digital 3-bit pulse width modulation (PWM). The designed clock cut-off circuit pauses the D-flipflops (D-ffs) after cutting off the clock at both 0 % and 100 % pulse width of PWM output for dimming. As a result, 10 transistors of the miniaturized control block were reduced and layout area of the optimized control block is 2,198.0µm 2 using Rohm 0.18µm standard CMOS model .The operation of control block of clock cut-off circuit with ADCL 3-bit digital PWM is confirmed by post-simulation of hspice. vR(t) and power dissipation PR(t) in Fig. 3 (a) are expressed in equation (1) , (2), and (3) , respectively, where τ is the rising time of input,  is unsynchronized period and   t u is the unit step function [11] [12] [13] [14] [15] [16] . The PWM is normally used for the dimming circuit. The ADCL digital 3-bit PWM is designed using ADCL gates. When input bits (LD0, LD1, LD2) are LLH, LHH, the output pulse width of PWM is about 33.3 %, 66.6 % and characteristics of ADCL, the adiabatic charging/discharge are confirmed respectively. The power consumption of ADCL digital PWM is lower than it of CMOS digital PWM through adiabatic charging/discharging operation. However, unnecessary operation at both dimming 0 % and 100 % of ADCL digital PWM output results in power consumption. The designed clock cut-off circuit pauses the D-ffs after cutting off the clock at both input-bit LLL (0 %) and HHH (100 %), and performs normal operation of the D -ffs at other case. circuit pauses the D-ffs after cutting off the clock at both 0 % and 100 % pulse width of PWM output. This shows the potential of the optimized ADCL digital PWM in future low-power OLED dimming systems. Moreover, at the Smart MIRAI House, the research results for the living environment of the near future are demonstrated and correlation between big data analysis and deep sleep are verified. Figure 9. Post-simulation Results of ADCL 3-bit PWM with the Clock Cut-off Circuit
doi:10.14257/ijsh.2016.10.9.30 fatcat:y3faleqhqvbubj6cng5pvirblm