A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is
25th ACM/IEEE, Design Automation Conference.Proceedings 1988.
In this paper an approach for timing simulation of bipolar ECX digital circuits is descibed. The approach is based on the development of a switch-level model of the transistor and on the representation of the circuit by a switch-graph. The circuit is partitioned into subcircuits, and symbolic logic expressions are then generated. which represent the logic states of the nodes in terms of subcircuit inputs and initial conditions. Timing information is computed using an analytical delay modeldoi:10.1109/dac.1988.14772 fatcat:5ynmcwjvxfdijfgq5dps2nbr24