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Study of full parallel RS(31,27) encoder for a 3.2 Gbps serial transmitter in 0.18 μm CMOS technology

G. Zhang, Q. Sun, T. Liu, D. Gong, B. You, L. Xiao, X. Sun, J. Ye, D. Yang, Y. Feng, J. Wang
2019 Journal of Instrumentation  

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2018 pre-print arXiv:1806.02173v1 fatcat:unqpbohpgnhqzglcifp5ip3h3y
This work presents the design of an RS(31,27) Reed Solomon encoder for a 3.2 Gbps serial transmitter in 0.18 um CMOS technology. The proposed encoder is designed with a novel full parallel structure optimized for high speed and high stability. One data frame contains 2 interleaved RS(31,27) codes and thus it can correct at most 20 bits of consecutive errors. A corresponding decoder is implemented on Xilinx Kintex-7 FPGA.
doi:10.1088/1748-0221/14/02/p02028 fatcat:eyyhwaavbnadjdd2lkdicdney4
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G. Zhang, Q. Sun, T. Liu, D. Gong, B. You, L. Xiao, X. Sun, J. Ye, D. Yang, Y. Feng, J. Wang. "Study of full parallel RS(31,27) encoder for a 3.2 Gbps serial transmitter in 0.18 μm CMOS technology." Journal of Instrumentation 14.02 (2019) P02028-P02028