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IACR Cryptology ePrint Archive
A system-on-chip (SoC) security can be weakened by exploiting the potential vulnerabilities of the intellectual property (IP) cores used to implement the design and interaction among the IPs. These vulnerabilities not only increase the security verification effort but also can increase design complexity and time-to-market. The design and verification engineers should be knowledgeable about potential vulnerabilities and threat models at the early SoC design life cycle to protect their designsdblp:journals/iacr/FarzanaFT21 fatcat:ngtr63o5vbddnnx6ioyerguqwm