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An Area-efficient and Protected Network Interface for Processing-In-Memory Systems

S.D. Mediratta, C. Steele, J. Sondeen, J. Draper
2005 IEEE International Symposium on Circuits and Systems  

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This paper describes the implementation of an areaefficient and protected user memory-mapped network interface, the pbuf (Parcel Buffer), for the Data IntensiVe Architecture (DIVA) processing-in-memory (PIM) system. This implementation of the pbuf in TSMC 0.18 µm CMOS technology displays an aggregate bi-directional throughput of 48.08Gbps, using low area (0.56 mm 2 ) and power consumption (32.30mW). These characteristics, especially the low area and power, have made the current implementation
more » ... ideal choice for assimilation in DIVA PIM systems, since low area and power are critical design requirements in the PIM philosophy. The pbuf implementation has been verified by the execution of a 2-PIM Transitive Closure benchmark at 140MHz on an HP Itanium2-based Long's Peak server containing DIMMs populated with DIVA-II PIM chips.
doi:10.1109/iscas.2005.1465246 dblp:conf/iscas/MedirattaSSD05 fatcat:gb5bsbvijvcwhbvyh5l3fwgoqa
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S.D. Mediratta, C. Steele, J. Sondeen, J. Draper. "An Area-efficient and Protected Network Interface for Processing-In-Memory Systems." 2005 IEEE International Symposium on Circuits and Systems 2951-2954